View 4X16E43V_1523824.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 features options marking ? operating temperature range commercial (0 c to +70 c) none extended (-40 c to +85 c) it note : 1. the ? # ? symbol indicates signal is active low. part number example: mem4X16E43Vtw-5 pin assignment (top view) v cc dq0 dq1 dq2 dq3 v cc dq4 dq5 dq6 dq7 nc v cc we# ras# nc nc nc nc a0 a1 a2 a3 a4 a5 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 v ss dq15 dq14 dq13 dq12 v ss dq11 dq10 dq9 dq8 nc v ss casl# cash# oe# nc nc nc/ a12 ? a11 a10 a9 a8 a7 a6 v ss key timing parameters speed t rc t rac t pc t aa t cac t cas -5 84ns 50ns 20ns 25ns 13ns 8ns -6 104ns 60ns 25ns 30ns 15ns 1 0ns 50-pin tsop 4 meg x 16 edo dram part numbers refresh part number addressing package 4X16E43Vtw-x 4 400-tsop 4x16e83vtw-x 8 400-tsop x = speed 4X16E43V 4x16e83v configuration 4 meg x 16 4 meg x 16 refresh 4k 8k row address 4k (a0-a11) 8k (a0-a12) column addressing 1k (a0-a9) 512 (a0-a8) ? a12 for "8k" version, nc for "4k" version. 4 meg x 16 edo dram edo dram 4X16E43V ? single +3.3v 0.3v power supply ? industry-standard x16 pinout, timing, functions, and package ? 12 row, 10 column addresses (4) 13 row, 9 column addresses (8) ? high-performance cmos silicon-gate process ? all inputs, outputs and clocks are lvttl-compatible ? extended data-out (edo) page mode access ? 4,096-cycle cas#-before-ras# (cbr) refresh distributed across 64ms ? self refresh for low-power data retention ? plastic package 50-pin tsop (400 mil) tw ? timing 50ns access -5 60ns access -6 ? refresh rates 4k 4 8k 8
2 a0- a11 ras# 12 12 10 refresh controller no. 1 clock generator v dd v ss 12 10 column- address buffer(10) row- address buffers (12) 4,096 1,024 column decoder 16 refresh counter row select row decoder 4,096 x 1,024 x 16 memory array complement select 1,024 x 16 4,096 x 16 no. 2 clock generator we# oe# dq0- dq15 16 16 data-out buffer casl# cas# cash# data-in buffer 16 sense amplifiers i/o gating functional block diagram 4X16E43V (12 row addresses) a0- a12 ras# 13 13 9 no. 2 clock generator refresh controller no. 1 clock generator vcc vss 13 we# 9 column- address buffer(9) row- address buffers (13) 8192 512 column decoder oe# dq0- dq15 16 16 16 16 refresh counter row select row decoder sense amplifiers i/o gating data-out buffer 8192 x 512 x 16 memory array complement select 512 x 16 8192 x 16 casl# cas# cash# data-in buffer functional block diagram 4x16e83v (13 row addresses) 4 meg x 16 edo dram
3 figure 1 word and byte write example stored data 1 1 0 1 1 1 1 1 ras# casl# we# x = not effective (don?t care) address 1 address 0 0 1 0 1 0 0 0 0 word write lower byte write cash# input data 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 x x x x x x x x input data 1 1 0 1 1 1 1 1 input data stored data 1 1 0 1 1 1 1 1 input data stored data 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 stored data 0 0 1 0 0 0 0 0 1 0 1 0 1 1 1 1 x x x x x x x x 1 0 1 0 1 1 1 1 upper byte (dq8-dq15) of word lower byte (dq0-dq7) of word general description the 4 meg x 16 dram is a high-speed cmos, dynamic random-access memory device containing 67,108,864 bits and designed to operate from 3v to 3.6v. the device is functionally organized as 4,194,304 locations containing 16 bits each. the 4,194,304 memory locations are arranged in 4,096 rows by 1,024 columns on the mem4X16E43Vtw . during read or write cycles, each location is uniquely addressed via the address bits: 12 row-address bits (a0-a11) and 10 column-address bits (a0-a9) on the mem4X16E43Vtw version. in addition, the byte and word accesses are supported via the two cas# pins (casl# and cash#). the cas# functionality and timing related to ad- dress and control functions (e.g., latching column addresses or selecting cbr refresh) is such that the internal cas# signal is determined by the first external cas# signal (casl# or cash#) to transition low and the last to transition back high. the cas# functional- ity and timing related to driving or latching data is such that each cas# signal independently controls the asso- ciated eight dq pins. the row address is latched by the ras# signal, then the column address is latched by cas#. this device provides edo-page-mode operation, allowing for fast successive data operations (read, write or read- modify-write) within a given row. the 4 meg x 16 dram must be refreshed periodi- cally in order to retain stored data. dram access each location in the dram is uniquely addressable, as mentioned in the general description. use of both cas# signals results in a word access via the 16 i/o pins (dq0-dq15). using only one of the two signals results in a byte access cycle. casl# transitioning low se- lects an access cycle for the lower byte (dq0-dq7), and cash# transitioning low selects an access cycle for 4 meg x 16 edo dram
4 the upper byte (dq8-dq15). general byte and word access timing is shown in figures 1 and 2. a logic high on we# dictates read mode, while a logic low on we# dictates write mode. during a write cycle, data-in (d) is latched by the falling edge of we or cas# (casl# or cash#), whichever occurs last. an early write occurs when we is taken low prior to either cas# falling. a late write or read- modify-write occurs when we falls after cas# (casl# or cash#) is taken low. during early write cycles, the data outputs (q) will remain high-z, regardless of the state of oe#. during late write or read-modify- write cycles, oe# must be taken high to disable the data outputs prior to applying input data. if a late write or read-modify-write is attempted while keeping oe# low, no write will occur, and the data outputs will drive read data from the accessed location. additionally, both bytes must always be of the same mode of operation if both bytes are active. a cas# precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. for example, an early write on one byte and a late figure 2 word and byte read example stored data 1 1 0 1 1 1 1 1 ras# casl# we# z = high-z address 1 address 0 0 1 0 1 0 0 0 0 word read lower byte read stored data 1 1 0 1 1 1 1 1 cash# output data 1 1 0 1 1 1 1 1 stored data 1 1 0 1 1 1 1 1 z z z z z z z z output data 1 1 0 1 1 1 1 1 output data 1 1 0 1 1 1 1 1 output data 1 1 0 1 1 1 1 1 stored data 1 1 0 1 1 1 1 1 upper byte (dq8-dq15) of word lower byte (dq0-dq7) of word 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 z z z z z z z z z z z z z z z z 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 write on the other byte are not allowed during the same cycle. however, an early write on one byte and a late write on the other byte, after a cas# precharge has been satisfied, are permissible. edo page mode dram read cycles have traditionally turned the output buffers off (high-z) with the rising edge of cas#. if cas# went high and oe# was low (active), the output buffers would be disabled. the 64mb edo dram offers an accelerated page mode cycle by elimi- nating output disable from cas# high. this option is called edo, and it allows cas# precharge time ( t cp) to occur without the output data going invalid (see read and edo-page-mode read waveforms). edo operates like any dram read or fast-page- mode read, except data is held valid after cas# goes high, as long as ras# and oe# are held low and we# is held high. oe# can be brought low or high while cas# and ras# are low, and the dqs will transition between valid data and high-z. using oe#, there are dram access ( continued ) 4 meg x 16 edo dram
5 figure 3 oe# control of dqs v v ih il cas# v v ih il ras# v v ih il addr row column (a) column (b) v v ih il oe# v v ioh iol open dq t od valid data (b) valid data (a) column (c) valid data (a) t oe valid data (c) column (d) valid data (d) t od t oehc t od t oep t oes the dqs go back to low-z if t oes is met. the dqs remain high-z until the next cas# cycle if t oehc is me t. the dqs remain high-z until the next cas# cycle if t oep is met. figure 4 we# control of dqs v v ih il cas# v v ih il ras# v v ih il addr row column (a) don?t care undefined v v ih il we# v v ioh iol open dq t wpz the dqs go to high-z if we# falls and, if t wpz is met, will remain high-z until cas# goes low with we# high (i.e., until a read cycle is initiated). v v ih il oe# valid data (b) t whz we# may be used to disable the dqs to prepare for input data in an early write cycle. the dqs will remain high-z until cas# goes low with we# high (i.e., until a read cycle is initiated). t whz column (d) valid data (a) column (b) column (c) input data (c) 4 meg x 16 edo dram
6 two methods to disable the outputs and keep them disabled during the cas# high time. the first method is to have oe# high when cas# transitions high and keep oe# high for t oehc thereafter. this will disable the dqs, and they will remain disabled (regardless of the state of oe# after that point) until cas# falls again. the second method is to have oe# low when cas# transitions high and then bring oe# high for a minimum of t oep anytime during the cas# high period. this will disable the dqs, and they will remain disabled (regardless of the state of oe# after that point) until cas# falls again (see figure 3). during other cycles, the outputs are disabled at t off time after ras# and cas# are high or at t whz after we# transitions low. the t off time is referenced from the rising edge of ras# or cas#, whichever occurs last. we# can also perform the function of disabling the output drivers under certain conditions, as shown in figure 4. edo-page-mode operations are always initiated wit h a ro w address strobed in by the ras# signal, followed by a column address strobed in by cas#, just like for single location accesses. however, subsequent column locations within the row may then be accessed at the page mode cycle time. this is accomplished by cycling cas# while holding ras# low and entering new column addresses with each cas# cycle. returning ras# high terminates the edo-page-mode operation. dram refresh the supply voltage must be maintained at the speci- fied levels, and the refresh requirements must be met in order to retain stored data in the dram. the refresh requirements are met by refreshing all rows in the 4 meg x 16 dram array at least once every 64ms (8,192 rows for 8 or 4,096 rows for 8). the recommended procedure is to execute 4,096 cbr refresh cycles, either uniformly spaced or grouped in bursts, every 64ms. the mem4X16E43Vtw refreshes one row for every cbr cycle. for either device, executing 4,096 cbr cycles will refresh the entire de vice. the cbr refresh will invoke the internal refresh counter for automatic ras# addressing. alternatively, ras#-only refresh capability is inherently provided. however, with this method, only one row is refreshed on each cycle. jedec strongly recommends the use of cbr refresh for this device. the self refresh mode is also available. the self refresh feature is initiated by performing a cbr refresh cycle and holding ras# low for the specified trass. the self refresh mode allows the user the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended refresh period of 128ms, or 31.25 s per cycle, when using a distributed cbr refresh. this refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. the self refresh mode is terminated by driving ras# high for a minimum time of t rps. this delay allows for the completion of any internal refresh cycles that may be in process at the time of the ras# low-to-high transition. if the dram controller uses a distributed cbr refresh sequence, a burst refresh is not required upon exiting self re fresh, however, if the controller is using ras# only or burst cbr refresh then a burst refresh using t rc (min) is required. edo page mode ( continued ) 4 meg x 16 edo dram
7 absolute maximum ratings* voltage on v cc relative to v ss ................ -1v to +4.6v voltage on nc, inputs or i/o pins relative to v ss ....................................... -1v to +4.6v operating temperature, t a (ambient) commercial ......................................... 0 c to +70 c extended (it) ................................. -40 c to +85 c** storage temperature (plastic) ............ -55 c to +150 c power dissipation ................................................... 1w *stresses greater than those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions (note: 1) (v cc = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v cc 3 3.6 v input high voltage : valid logic 1; all inputs, i/os and any nc v ih 2v cc + 0.3 v 35 input low voltage : valid logic 0; all inputs, i/os and any nc v il -0.3 0.8 v 3 5 input leakage current: any input at v in (0v v in v cc + 0.3v) ; i i -2 2 a 3 6 all other pins not under test = 0v output high voltage : i out = -2ma v oh 2 . 4 ? v output low voltage : i out = 2ma v ol ? 0.4 v output leakage current: any output at v out (0v v out v cc + 0.3v); i oz -5 5 a dq is disabled and in high-z state 4 meg x 16 edo dram < _ < _ < _ < _
8 icc operating conditions and maximum limits (notes: 1, 2, 3, 5, 6) (v cc = +3.3v 0.3v) parameter/condition symbol speed 4 k 8k units notes standby current: ttl i cc 1 all 1 1 m a (ras# = cas# = v ih ) standby current: cmos (ras# = cas# 3 v cc - 0.2v; dqs may be left open; i cc 2 a l l 500 500 a other inputs: v in 3 v cc - 0.2v or v in 0.2v) operating current: random read/write i cc 3 -5 150 115 ma 26 average power supply current -6 165 130 (ras#, cas#, address cycling: t rc = t rc [min]) operating current: edo page mode i cc 4 -5 120 120 ma 26 average power supply current -6 125 125 (ras# = v il , cas#, address cycling: t pc = t pc [min]) refresh current: ras#-only i cc 5 -5 150 115 ma 22 average power supply current -6 165 130 (ras# cycling, cas# = v ih : t rc = t rc [min]) refresh current: cbr i cc 6 -5 150 150 ma 4 , 7 , average power supply current -6 165 165 23 (ras#, cas#, address cycling: t rc = t rc [min]) refresh current: extended cc 7 a l l 400 400 a 4 , 7 , average power supply current: cas# = 0.2v or cbr cycling; 23, 37 ras# = t ras (min); we# = v cc - 0.2v; a0-a10, oe# and d in = v cc - 0.2v or 0.2v (d in may be left open); t rc = 125 s refresh current: self cc 8 a l l 350 350 a 4 , 7 , average power supply current: cbr with ras# 3 t rass (min) 3 7 and cas# held low; we# = v cc - 0.2v; a0-a10, oe# and d in = v cc - 0.2v or 0.2v (d in may be left open) max 4 meg x 16 edo dram
9 ac electrical characteristics (notes: 5, 6, 7, 8, 9, 10, 11, 12) (v cc = +3.3v 0.3v) ac characteristics -5 -6 parameter symbol min m a x min m a x units notes access time from column address t a a 25 30 n s column-address setup to cas# precharge t a c h 12 15 n s column-address hold time (referenced to ras#) t a r 38 45 n s column-address setup time t asc 0 0 n s 2 8 row-address setup time t asr 0 0 n s 2 8 column address to we# delay time t awd 4 2 4 9 n s 1 8 access time from cas# t c a c 13 15 n s 29 column-address hold time t cah 8 1 0 n s 2 8 cas# pulse width t cas 8 10,000 1 0 10,000 n s 30, 32 cas# low to ? don?t care ? during self refresh t c h d 15 15 n s cas# hold time (cbr refresh) t chr 8 1 0 n s 4, 31 last cas# going low to first cas# to return high t clch 5 5 n s 3 1 cas# to output in low-z t clz 0 0 n s 2 9 data output hold after cas# low t coh 3 3 n s cas# precharge time t c p 8 1 0 n s 13, 33 access time from cas# precharge t c p a 28 35 n s 29 cas# to ras# precharge time t crp 5 5 n s 3 1 cas# hold time t csh 3 8 4 5 n s 3 1 cas# setup time (cbr refresh) t csr 5 5 n s 4, 28 cas# to we# delay time t cwd 2 8 3 5 n s 18, 28 write command to cas# lead time t cwl 8 1 0 n s 3 1 data-in hold time t dh 8 1 0 n s 19, 29 data-in setup time t d s 0 0 n s 19, 29 output disable t o d 0 1 2 0 1 5 n s 24, 25 output enable time t o e 12 15 n s 20 oe# hold time from we# during t oeh 8 1 0 n s 2 5 read-modify-write cycle oe# high hold time from cas# high t oehc 5 1 0 n s oe# high pulse width t oep 5 5 n s oe# low to cas# high setup time t oes 4 5 n s output buffer turn-off delay t off 0 1 2 0 1 5 n s 17, 24, 29 oe# setup prior to ras# during hidden refresh cycle t ord 0 0 n s capacitance (note: 2) parameter symbol m a x units input capacitance: address pins c i 15 p f input capacitance: ras#, cas#, we#, oe# c i 27 p f input/output capacitance: dq c io 7p f 4 meg x 16 edo dram
10 ac electrical characteristics (notes: 5, 6, 7, 8, 9, 10, 11, 12) (v cc = +3.3v 0.3v) ac characteristics -5 -6 parameter symbol min m a x min m a x units notes edo-page-mode read or write cycle time t pc 20 25 n s 34 edo-page-mode read-write cycle time t prwc 4 7 5 6 n s 3 4 access time from ras# t r a c 50 60 n s ras# to column-address delay time t rad 9 1 2 n s 1 5 row address hold time t rah 7 1 0 n s ras# pulse width t ras 5 0 10,000 6 0 10,000 n s ras# pulse width (edo page mode) t rasp 5 0 125,000 6 0 125,000 n s ras# pulse width during self refresh t rass 100 100 s random read or write cycle time t r c 8 4 104 n s ras# to cas# delay time t rcd 1 1 1 4 n s 14, 28 read command hold time (referenced to cas#) t rch 0 0 n s 16, 30 read command setup time t rcs 0 0 n s 2 8 refresh period t r e f 6 4 6 4 m s 22, 23 refresh period (self refresh) t ref 128 128 m s 2 3 ras# precharge time t rp 30 40 n s ras# to cas# precharge time t rpc 5 5 n s ras# precharge time exiting self refresh t rps 9 0 105 n s read command hold time (referenced to ras#) t rrh 0 0 n s 1 6 ras# hold time t rsh 1 3 1 5 n s 3 5 read-write cycle time t rwc 116 140 n s ras# to we# delay time t rwd 6 7 7 9 n s 1 8 write command to ras# lead time t r w l 13 15 n s transition time (rise or fall) t t2 5 0 2 5 0 n s write command hold time t w c h 8 10 n s 35 write command hold time (referenced to ras#) t w c r 38 45 n s we# command setup time t w c s 0 0 n s 18, 28 we# to outputs in high-z t whz 1 2 1 5 n s write command pulse width t wp 5 5 n s we# pulse widths to disable outputs t wpz 1 0 1 0 n s we# hold time (cbr refresh) t wrh 8 1 0 n s we# setup time (cbr refresh) t wrp 8 1 0 n s 4 meg x 16 edo dram
11 edo dram notes 1. all voltages referenced to v ss . 2 . this parameter is sampled. v cc = +3.3v; f = 1 mhz; t a = 25 c. 3. i cc is dependent on output loading and cycle rates. specified values are obtained with mini- mum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. an initial pause of 100 s is required after power- up, followed by eight ras# refresh cycles (ras#- only or cbr with we# high), before proper device operation is ensured. the eight ras# cycle wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 2.5ns. 8. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il (or between v il and v ih ). 9. in addition to meeting the transition rate specification, all input signals must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 10. if cas# and ras# = v ih , data output is high-z. 11. if cas# = v il , data output may contain data from the last valid read cycle. 12. measured with a load equivalent to two ttl gates and 100pf; and v ol = 0.8v and v oh = 2v. 13. if cas# is low at the falling edge of ras#, output data will be maintained from the previous cycle. to initiate a new cycle and clear the data- out buffer, cas# must be pulsed high for t cp. 14. the t rcd (max) limit is no longer specified. t rcd (max) was specified as a reference point only. if t rcd was greater than the specified t rcd (max) limit, then access time was controlled exclusively by t cac ( t rac [min] no longer applied). with or without the t rcd limit, t aa and t cac must always be met. 15. the t rad (max) limit is no longer specified. t rad (max) was specified as a reference point only. if t rad was greater than the specified t rad (max) limit, then access time was controlled exclusively by t aa ( t rac and t cac no longer applied). with or without the t rad (max) limit, t aa, t rac, and t cac must always be met. 1 6 . either t rch or t rrh must be satisfied for a read cycle. 17. t off (max) defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . 18. t wcs, t rwd, t awd, and t cwd are not restrictive operating parameters. t wcs applies to early write cycles. if t wcs > t wcs (min), the cycle is an early write cycle and the data output will remain an open circuit throughout the entire cycle. t rwd, t awd, and t cwd define read- modify-write cycles. meeting these limits allows for reading and disabling output data and then applying input data. oe# held high and we# taken low after cas# goes low results in a late write (oe#-controlled) cycle. t wcs, t rwd, t cwd, and t awd are not applicable in a late write cycle. 19. these parameters are referenced to cas# leading edge in early write cycles and we# leading edge in late write or read-modify-write cycles. 20. if oe# is tied permanently low, late write, or read-modify-write operations are not possible. 21. a hidden refresh may also be performed after a write cycle. in this case, we# is low and oe# is high. 22. ras#-only refresh requires that all 8,192 rows of the arc8v4m16e or all 4,096 rows of the 4X16E43V be refreshed at least once every 64ms. 23. cbr refresh for either device requires that at least 4,096 cycles be completed every 64ms. 24. the dqs go high-z during read cycles once t od or t off occur. if cas# stays low while oe# is brought high, the dqs will go high-z. if oe# is brought back low (cas# still low), the dqs will provide the previously read data. 25. late write and read-modify-write cycles must have both t od and t oeh met (oe# high during write cycle) in order to ensure that the output buffers will be open during the write cycle. if oe# is taken back low while cas# remains low, the dqs will remain open. 26. column address changed once each cycle. 27. the first casx# edge to transition low. 4 meg x 16 edo dram
12 notes ( continued ) 2 8 . output parameter (dqx) is referenced to corresponding cas# input; dq0-dq7 by casl# and dq8-dq15 by cash#. 29. each casx# must meet minimum pulse width. 30. the last casx# edge to transition high. 31. last falling casx# edge to first rising casx# edge. 32. last rising casx# edge to first falling casx# edge. 33. last rising casx# edge to next cycle?s last rising casx# edge. 34. last casx# to go low. 35. v ih overshoot: v ih (max) = v cc + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. 36. nc pins are assumed to be left floating and are not tested for leakage. 37. self refresh and extended refresh for either device requires that at least 4,096 cycles be completed every 128ms. 4 meg x 16 edo dram
13 timing parameters -5 -6 symbol m i n max m i n max units t aa 25 30 ns t ach 12 15 ns t a r 38 45 ns t asc 0 0 n s t asr 0 0 n s t c a c 13 15 ns t cah 8 1 0 n s t cas 8 10,000 10 10,000 n s t clch 5 5 n s t clz 0 0 n s t crp 5 5 n s t csh 38 45 ns t od 0 1 2 0 1 5 n s read cycle note: 1. t off is referenced from rising edge of ras# or cas#, whicheve r occurs last. t rrh t clz t cac t rac t aa valid data open t off t rch row t rcs t asc t rah t rad t ar t cah t rcd t cas t rsh t csh t rp t rc t ras t crp t asr row open ras# v v ih il v v ih il addr v v ih il dq v v oh ol v v ih il t od t oe oe# v v ih il column cas# we# note 1 t ach don?t care undefined -5 -6 symbol m i n max m i n max units t o e 12 15 ns t off 0 1 2 0 1 5 n s t r a c 50 60 ns t rad 9 1 2 n s t rah 7 1 0 n s t ras 50 10,000 60 10,000 n s t rc 84 104 n s t r c d 11 14 ns t rch 0 0 n s t rcs 0 0 n s t r p 30 40 ns t rrh 0 0 n s t rsh 13 15 ns 4 meg x 16 edo dram
14 early write cycle don?t care undefined v v ih il valid data row column row t ds t wp t wch t wcs t wcr t rwl t cwl t cah t asc t rah t asr t rad t ar t cas t rsh t csh t rcd t crp t ras t rc t rp v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t dh we# cas# t ach -5 -6 symbol m i n max m i n max units t rad 9 1 2 n s t rah 7 1 0 n s t ras 50 10,000 60 10,000 n s t rc 84 104 n s t r c d 11 14 ns t r p 30 40 ns t rsh 13 15 ns t r w l 13 15 ns t wch 8 1 0 n s t w c r 38 45 ns t wcs 0 0 n s t wp 5 5 n s timing parameters -5 -6 symbol m i n max m i n max units t ach 12 15 ns t a r 38 45 ns t asc 0 0 n s t asr 0 0 n s t cah 8 1 0 n s t cas 8 10,000 10 10,000 n s t clch 5 5 n s t crp 5 5 n s t csh 38 45 ns t cwl 8 1 0 n s t dh 8 1 0 n s t ds 0 0 n s edo dram 4 meg x 16 edo dram
15 read-write cycle (late write and read-modify-write cycles ) valid d out valid d in row column row v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# open open t oe t od t cac t rac t aa t clz t ds t dh t awd t wp t rwl t cwl t cwd t rwd t rcs t asc t cah t ar t asr t rad t crp t rcd t cas t rsh t csh t ras t rwc t rp t rah oe# t oeh we# t ach cas# don?t care undefined -5 -6 symbol m i n max m i n max units t ds 0 0 n s t od 0 1 2 0 1 5 n s t o e 12 15 ns t oeh 8 1 0 n s t r a c 50 60 ns t rad 9 1 2 n s t rah 7 1 0 n s t ras 50 10,000 60 10,000 n s t r c d 11 14 ns t rcs 0 0 n s t r p 30 40 ns t rsh 13 15 ns t r w c 116 140 n s t rwd 67 79 ns t r w l 13 15 ns t wp 5 5 n s timing parameters -5 -6 symbol m i n max m i n max units t aa 25 30 ns t ach 12 15 ns t a r 38 45 ns t asc 0 0 n s t asr 0 0 n s t awd 42 49 ns t c a c 13 15 ns t cah 8 1 0 n s t cas 8 10,000 10 10,000 n s t clch 5 5 n s t clz 0 0 n s t crp 5 5 n s t csh 38 45 ns t cwd 28 35 ns t cwl 8 1 0 n s t dh 8 1 0 n s 4 meg x 16 edo dram
16 timing parameters -5 -6 symbol m i n max m i n max units t aa 25 30 ns t ach 12 15 ns t a r 38 45 ns t asc 0 0 n s t asr 0 0 n s t c a c 13 15 ns t cah 8 1 0 n s t cas 8 10,000 10 10,000 n s t clch 5 5 n s t clz 0 0 n s t coh 3 3 n s t cp 8 1 0 n s t cpa 28 35 ns t crp 5 5 n s t csh 38 45 ns t od 0 1 2 0 1 5 n s edo-page-mode read cycle valid data valid data valid data column column column row row don?t care undefined t od t cah t asc t cp t rsh t cp t cp t cas t rcd t crp t pc t csh t rasp t rp t cah t asc t cah t asc t ar t rah t rad t asr t rcs t rrh t rch t off t cac t cpa t aa t clz t cac t cpa t aa t cac t rac t aa t clz t oe t od t oe t od open open v v ih il v v ih il addr v v ih il v v ih il dq v v oh ol v v ih il ras# oe# t cas t cas cas# we# t coh t oep t oehc t oes t oes t ach t ach t ach -5 -6 symbol m i n max m i n max units t o e 12 15 ns t oehc 5 1 0 n s t oep 5 5 n s t oes 4 5 n s t off 0 1 2 0 1 5 n s t p c 20 25 ns t r a c 50 60 ns t rad 9 1 2 n s t rah 7 1 0 n s t rasp 50 125,000 60 125,000 ns t r c d 11 14 ns t rch 0 0 n s t rcs 0 0 n s t r p 30 40 ns t rrh 0 0 n s t rsh 13 15 ns 4 meg x 16 edo dram
17 timing parameters -5 -6 symbol m i n max m i n max units t ach 12 15 ns t a r 38 45 ns t asc 0 0 n s t asr 0 0 n s t cah 8 1 0 n s t cas 8 10,000 10 10,000 n s t clch 5 5 n s t cp 8 1 0 n s t crp 5 5 n s t csh 38 45 ns t cwl 8 1 0 n s t dh 8 1 0 n s t ds 0 0 n s edo-page-mode early write cycle t ds t dh t ds t dh t ds t dh t wcr valid data valid data valid data t rwl t wp t cwl t wch t wcs t wp t cwl t wch t wcs t wp t cwl t wch t wcs t cah t asc t cah t asc t cah t asc t rah t asr t rad t ach t ach t ach t ar column column column row row t cp t cas t rsh t cp t cas t cp t cas t rcd t crp t pc t csh t rasp t rp v v ih il cas# v v ih il addr v v ih il we# v v ih il dq v v ioh iol ras# don?t care undefined -5 -6 symbol m i n max m i n max units t p c 20 25 ns t rad 9 1 2 n s t rah 7 1 0 n s t rasp 50 125,000 60 125,000 ns t r c d 11 14 ns t r p 30 40 ns t rsh 13 15 ns t r w l 13 15 ns t wch 8 1 0 n s t w c r 38 45 ns t wcs 0 0 n s t wp 5 5 n s 4 meg x 16 edo dram
18 edo-page-mode read-write cycle (late write and read-modify-write cycles ) don?t care undefined t t od t oe t od t oe t od t oe open d out valid d in valid d out valid d in valid d out valid d in valid open t dh t ds t aa t cpa t clz t cac t dh t ds t aa t cpa t clz t cac t dh t ds t aa t clz t cac t rac t wp t cwl t rwl t cwd t awd t wp t cwl t cwd t awd t wp t cwl t cwd t awd t rcs t rwd t asr t rah t asc t rad t ar t cah t asc t cah t asc t cah t cp t rsh t cp t rp t rasp t cp t rcd t csh t pc t crp row column column column row v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t prwc oeh t cas t cas t cas we# casl#/cash# note 1 note: 1. t pc is for late write cycles only. -5 -6 symbol m i n max m i n max units t ds 0 0 n s t od 0 1 2 0 1 5 n s t o e 12 15 ns t oeh 8 1 0 n s t p c 20 25 ns t prwc 47 56 n s t r a c 50 60 ns t rad 9 1 2 n s t rah 7 1 0 n s t rasp 50 125,000 60 125,000 ns t r c d 11 14 ns t rcs 0 0 n s t r p 30 40 ns t rsh 13 15 ns t rwd 67 79 ns t r w l 13 15 ns t wp 5 5 n s timing parameters -5 -6 symbol m i n max m i n max units t aa 25 30 ns t a r 38 45 ns t asc 0 0 n s t asr 0 0 n s t awd 42 49 ns t c a c 13 15 ns t cah 8 1 0 n s t cas 8 10,000 10 10,000 n s t clch 5 5 n s t clz 0 0 n s t cp 8 1 0 n s t cpa 28 35 ns t crp 5 5 n s t csh 38 45 ns t cwd 28 35 ns t cwl 8 1 0 n s t dh 8 1 0 n s 4 meg x 16 edo dram
19 edo-page-mode read early write cycle (pseudo read-modify-write) v v ih il v v ih il ras# v v ih il addr v v ih il we# t rasp t rp row column (a) column (n) row v ih il oe# v v ioh iol t crp t csh t cas t rcd t asr t rah t rad t asc t ar t cah t asc t cah t asc t cah t cp t rsh valid data in t rcs t rch t wcs t oe valid data (b) valid data (a) t whz t cac t cpa t aa t cac t aa open dq t pc rac t t coh t wch t ds t dh t pc column (b) t ach cas# t cas t cas t cp t cp don?t care undefined -5 -6 symbol m i n max m i n max units t o e 12 15 ns t p c 20 25 ns t r a c 50 60 ns t rad 9 1 2 n s t rah 7 1 0 n s t rasp 50 125,000 60 125,000 ns t r c d 11 14 ns t rch 0 0 n s t rcs 0 0 n s t r p 30 40 ns t rsh 13 15 ns t wch 8 1 0 n s t wcs 0 0 n s t whz 12 15 ns timing parameters -5 -6 symbol m i n max m i n max units t aa 25 30 ns t ach 12 15 ns t a r 38 45 ns t asc 0 0 n s t asr 0 0 n s t c a c 13 15 ns t cah 8 1 0 n s t cas 8 10,000 10 10,000 n s t coh 3 3 n s t cp 8 1 0 n s t cpa 28 35 ns t crp 5 5 n s t csh 38 45 ns t dh 8 1 0 n s t ds 0 0 n s 4 meg x 16 edo dram
20 read cycle (with we#-controlled disable) t clz t cac t rac t aa valid data open t rch t rcs t asc t rah t rad t ar t cah t rcd t cas t csh t crp t asr row open ras# v v ih il v v ih il addr v v ih il dq v v oh ol v v ih il t od t oe oe# v v ih il column we# t whz t wpz t cp t asc t rcs column t clz casl#/cash# don?t care undefined -5 -6 symbol m i n max m i n max units t od 0 1 2 0 1 5 n s t o e 12 15 ns t r a c 50 60 ns t rad 9 1 2 n s t rah 7 1 0 n s t r c d 11 14 ns t rch 0 0 n s t rcs 0 0 n s t whz 12 15 ns t w p z 10 10 ns timing parameters -5 -6 symbol m i n max m i n max units t aa 25 30 ns t a r 38 45 ns t asc 0 0 n s t asr 0 0 n s t c a c 13 15 ns t cah 8 1 0 n s t cas 8 10,000 10 10,000 n s t clz 0 0 n s t cp 8 1 0 n s t crp 5 5 n s t csh 38 45 ns 4 meg x 16 edo dram
21 ras#-only refresh cycle (oe# and we# = don?t care ) row v v ih il v v ih il addr v v ih il ras# t rc t ras t rp t crp t asr t rah row open q v v oh ol t rpc casl#/cash# cbr refresh cycle (addresses and oe# = don?t care) t rp v v ih il ras# t ras open t chr t csr v v ih il casl#/cash# dq t rp t ras t rpc t csr t rpc t chr t cp v v ih il t wrp t wrh t wrp t wrh we# don?t care undefined v v oh ol note 1 -5 -6 symbol m i n max m i n max units t ras 50 10,000 60 10,000 n s t rc 84 104 n s t r p 30 40 ns t rpc 5 5 n s t wrh 8 1 0 n s t wrp 8 1 0 n s timing parameters -5 -6 symbol m i n max m i n max units t asr 0 0 n s t chr 8 1 0 n s t cp 8 1 0 n s t crp 5 5 n s t csr 5 5 n s t rah 7 1 0 n s note: 1 . end of first cbr refresh cycle. 4 meg x 16 edo dram
22 hidden refresh cycle 1 (we# = high; oe# = low) don?t care undefined t clz t off open valid data open column row t cac t rac t aa t cah t asc t rah t asr t rad t ar t crp t rcd t rsh t ras t rc t rp t chr t ras dqx v v ioh iol v v ih il addr v v ih il v v ih il ras# v v ih il t oe t od oe# t ord casl#/cash# -5 -6 symbol m i n max m i n max units t o e 12 15 ns t off 0 1 2 0 1 5 n s t ord 0 0 n s t r a c 50 60 ns t rad 9 1 2 n s t rah 7 1 0 n s t ras 50 10,000 60 10,000 n s t r c d 11 14 ns t r p 30 40 ns t rsh 13 15 ns timing parameters -5 -6 symbol m i n max m i n max units t aa 25 30 ns t a r 38 45 ns t asc 0 0 n s t asr 0 0 n s t c a c 13 15 ns t cah 8 1 0 n s t chr 8 1 0 n s t clz 0 0 n s t crp 5 5 n s t od 0 1 2 0 1 5 n s note: 1. a hidden refresh may also be performed after a write cycle. in this case, we# is low and oe# is high. 4 meg x 16 edo dram
23 self refresh cycle (addresses and oe# = don?t care) v v ih il ras# t rass open v v ih il v v oh ol dq t rpc t chd t rps t rpc t rp t cp casl#/ cash# t wrh t wrp we# v v ih il t wrh t wrp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) note 1 t csr don?t care undefined t cp note 2 ( ) ( ) ( ) ( ) timing parameters -5 -6 symbol m i n max m i n max units t chd 15 15 ns t clch 5 5 n s t cp 8 1 0 n s t csr 5 5 n s t rass 1 0 0 1 0 0 n s t r p 30 40 n s t rpc 5 5 n s t rps 90 105 n s t wrh 8 1 0 n s t wrp 8 1 0 n s note: 1. once t rass (min) is met and ras# remains low, the dram will enter self refresh mode. 2 . once t rps is satisfied, a complete burst of all rows should be exe cuted if ras#-only or burst cbr refresh is used. -5 -6 symbol m i n max m i n max units 4 meg x 16 edo dram
24 50-pin plastic tsop (400 mil) .10 10.21 10.11 .45 .30 .80 typ 50 12 5 see det ail a max .25 det ail a gage plane pin #1 id .20 .25 .18 .13 21.04 20.88 11.86 11.66 .80 typ .60 .40 .88 typ note: 1. all dimensions in millimeters max or typical where noted. min 2 . package width and length do not include mold protrusion; all owable mold protrusion is .25mm per side. 4 meg x 16 edo dram

▲Up To Search▲

Price & Availability of 4X16E43V

	To Download 4X16E43V Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .